The present invention relates to a decoded signal comparison circuit formed in a semiconductor integrated circuit, and more particularly to a circuit for comparing two sets of decoded digital signals to detect coincidence/non-coincidence of bit structures, i.e., a decoded signal comparison circuit used as an address comparator for detecting coincidence of bit structures of a write address decoded signal and a read address decoded signal in a high-speed synchronous SRAM (static random access memory) having, for example, a late write specification.
The late write specification, which comes to be used in a high-speed synchronous SRAM in recent years, will be described with reference to a timing chart shown in FIG. 1.
In FIG. 1, "R", "W" and "dummy" represent a read cycle, a write cycle, and a dummy cycle.
As shown in FIG. 1, write data D3 is input in the cycle next to that when a write address Add3 is input, and write data D4 is input in the cycle next to that when a write address Add4 is input. A write operation inside a memory is performed in or after the cycle next to the cycle when the write data is input, not in the cycle when the write address is input.
In this case, a read address Add5 can be input in a cycle when the write data D4 is input. The read address Add5 is input and stored in a register, immediately after the write data D4 is input. In the cycle when the read address Add5 is input, a write operation inside the memory is not performed. The write data D4 input in this cycle and the write address Add4 input in the preceding cycle are stored in the registers.
An operation of writing the stored write data D4 is performed in the next write cycle.
More specifically, in a cycle when a read address Add6 is input, the read address Add6 is compared with the write address Add5 input and stored in the preceding cycle by means of an address comparison circuit. If the bit signals of the addresses coincide, the write data D4 input and stored in the preceding cycle is output as read data.
Generally, in the synchronous SRAM, since an address register and a read data register are arranged with a memory array interposed therebetween, the operation frequency of the memory is determined by a maximum value of a delay time of a signal transferred between the registers. Therefore, it is preferable that the address register storing the aforementioned two sets of addresses Add5 and Add6 be located near the memory cell array in an address path. Accordingly, it is preferable that the address comparison circuit be also located near the address path.
For this reason, conventionally, as shown in FIG. 2 address comparison circuits CPi (i=1 to 36) are inserted to output sides of a plurality of predecoders 2ai (i=1 to 9) for decoding an 18-bit address input in units of two bits.
First address inputs A0 and A1 are input to a predecoder 2a1. Decode outputs of four bits from the predecoder 2a1 are temporarily stored in first registers 11i (i=1 to 4). Then, bit signals of the first registers 11i (i=1 to 4) are stored in second registers 12i (i=1 to 4). Bit signals output from a pair of registers 11i and 12i are compared by a bit line comparison circuit CPi (i=1 to 4).
Next, second address inputs A2 and A3 are input to a predecoder 2a2. Decode outputs of four bits from the predecoder 2a2 are stored in first and second registers 11i and 12i. Then, bit signals output from a pair of registers 11i and 12i are compared by a bit signal comparison circuit CPi (i=1 to 4).
Comparison outputs from the bit signal comparison circuits CPi (i=1 to 4) provided for each predecoder 2ai (i=1 to 9) are input to a global comparison circuit 130, which detects whether the outputs coincide with each other. Thus, it is detected whether all bits of the two sets of address inputs (the first and second address inputs which are time-sequentially input) coincide or not.
In FIG. 2, one of the two bit signals output from the pair of registers 11i and 12i is selected by a multiplexer 16i (i=1 to 4), and thereafter input to and decoded by a main decoder 2b.
In the above structure, according to the conventional art, an exclusive OR gate, for example, as shown in FIG. 3, is used as the bit signal comparison circuit CPi (i=1 to 4). The exclusive OR gate, which operates based on a truth table as shown in FIG. 4, is comparatively complicated in structure and large in circuit scale. In addition, it consumes a comparatively large amount of current. If every predecoder 2ai (i=1 to 9) requires four exclusive OR gates as described above, i.e., 36 exclusive OR gates in total are required, the amount of power consumption and the area of the pattern layout must be increased.
Moreover, the global comparison circuit 130 must have a number of gate circuits to which a great number of signals are input, as shown in FIG. 5, in order to detect coincidence or non-coincidence of bit outputs from the aforementioned 36 exclusive OR gates.
As a result, the address comparison circuit including the conventional global comparison circuit causes an increase in signal delay time (comparing operation time), power consumption and the area of the pattern layout.
As described above, the conventional decoded signal comparison circuit for comparing two sets of decoded digital signals requires bit signal comparison circuits CPi (i=1 to 4) having a number of exclusive OR gates of a comparatively complicated structure and a global comparison circuit to which a great number of signals are input. Therefore, the signal comparison circuit has problems that it requires a long comparison operation time, a large amount of power, and a large area for the pattern layout.
A semiconductor device in which the late write system is realized in a synchronous SRAM is disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 8-45277.